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Re:TCP Stack support for LAN9303 (Andy123)

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Thank you Howard
Again, I just started my research and I completely missed possible SD bottleneck concentrating on the Ethernet side of the issue
Now it appear that it Ethernet side will not be a problem.
I will shift my research to SD now.
SD card area is not the one I am very familiar with. FAT system may be another issue
From what I remember ~10 years ago, my old company was forced to by Microsoft FAT license to use FAT formatted CF cards in their products, I am not sure what situation is today with SDs and I don't want to deal with any licensing or any other legal issues.
 
In any case I really appreciate your help for steering in SD direction.
Thanks! 

Re:TCP Stack support for LAN9303 (Andy123)

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I want to bring this old thread back since I finally got time to work on this and made a functional prototype.
 
Yes, but there is no native support for the LAN9303. You'll have to write your own "PHY driver" for it in order to control the non-IEEE 802.3 features, like port mirroring. Fortunately, this will likely be extremely simple. See for example, the ETHPIC32ExtPhySMSC8720.c file.

I was able to read and write registers 0-31 of all 3 PHYs, but I am not sure how to access registers that mapped to higher numbers?
 

Re:TCP Stack support for LAN9303 (Andy123)

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I figured this out - manual page 127:)
It uses combined fields of Phy address and attribute number to create a memory address 
Two 16 bit operations require to get 32 bit value
I did not try this yet, but it looks straigh forward

Re:TCP Stack support for LAN9303 (roundrocktom)

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Andy - How are you managing the SMSC LAN9303?   SMI  or I2C?
 
Web Page:
http://www.smsc.com/Produ...tches/LAN9303_LAN9303M
 
Click "download" to get to the documents (datasheet, reference design).
LAN9303/LAN9303i datasheet  (revision 1.5  07-08-11)
 
section 2.3.4 management modes, there are four management modes:
P0_Mode [2:0]  and MNGT1_LED4P & MNGT0_LED3PST will set the modes.
Table 3.4 Port 0 MII/RMII pins will list how to set Port 0 straps
 
 
Nice thing about the LAN9303 is you can set it up in Virtual PHY mode, which allows the software that was running the LAN8720 to think it is a just a single port PHY sitting there.  [registers 0-15 are common to all IEEE PHys;  16-31 are device specific....  LAN9303 Virtual PHY uses 0-6 & 31]   This makes life easy to get up and running,  just make sure your strapping is correct for things like PHY address and strapping MII/RMII, etc.
 
Let me know what mode you are using, glad to give pointers.
 
 
 
 
 
 
 
 
 
 
 

Re:TCP Stack support for LAN9303 (Andy123)

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 roundrocktom
 
As I pointed in my previous post - I am all set, I already moved on
My prototype with LAN9303 is working great and I am doing other tasks now based on the switch functionality
 
to answer your questions:
Yes, I set it for virtual PHY and using SMI to manage it.
I can read and write any registers without any problems
Earlier I had some issues with 18xx regisrters but quicky realized that I must read both High and Low of 32 bit register even only Low portion has data 
  

 

Re:TCP Stack support for LAN9303 (pluto55)

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Hi, Andy:
I use STM32+LAN9303 for my project , the device mode of LAN9303 is SMI Managed Mode & RMII PHY Mode(Table 4.3 from Revision 1.3),
I want to write SWE_BCST_THROT to configure the broadcast input rate throttling, but I don't know how to
write 1848h,can you give me one example
thank you very much

Re:TCP Stack support for LAN9303 (Andy123)

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I am not sure about STM32, here are routines I have for PIC32 and LAN9303.

for indirect write to CSR reg that is not mapped to memory see page 162 of the user manual
writes also can be done via regs 200-2dc page 167

unsigned long EthReadRegister(int reg) {
  unsigned long temp;
  unsigned int phy, address;
  phy=((reg & 0x3fc)>>6)| 0x10;
  address= (reg & 0x3c)>>1;
  EthMIIMReadStart(address+1, phy);
  temp= EthMIIMReadResult()<<16;
  EthMIIMReadStart(address, phy);
  return temp+EthMIIMReadResult();
 }
 
 
void EthWriteRegister(int reg, unsigned long value) {
  unsigned int temp, phy, address;
  phy=((reg & 0x3fc)>>6)| 0x10;
  address= (reg & 0x3c)>>1;
  temp= (unsigned int)(value>>16);
  EthMIIMWriteStart(address+1, phy, temp);   
  temp=(unsigned int)(value&0xffff);
  EthMIIMWriteStart(address, phy, temp );   
}
 
// indirect write to CSR reg that is not mapped to memory
// See page 162
 
unsigned long EthReadCSRRegister(int reg) {
    EthWriteRegister(0x1b0,(0xc00f0000 | reg));
    while(EthReadRegister(0x1b0) & 0x80000000); // wait for busy to clear
    return EthReadRegister(0x1ac);
}
  
void EthWriteCSRRegister(int reg, unsigned long value) {
    EthWriteRegister(0x1ac,value); // prepare data
    EthWriteRegister(0x1b0,(0x800f0000 | reg)); // write command
    while(EthReadRegister(0x1b0) & 0x80000000); // wait for busy to clear
}
 
// writes also can be done via regs 200-2dc page 167


Re:TCP Stack support for LAN9303 (pluto55)

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   thank you for your attention, I can't find the defination of these three functions:EthMIIMReadResult()、EthMIIMReadStart()、EthMIIMWriteStart().
does these functions defined in the lib for PIC32 from Microchip?
  would you please tell me the defination of the functions?
 
  

Re:TCP Stack support for LAN9303 (Andy123)

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Functions:EthMIIMReadResult()、EthMIIMReadStart()、EthMIIMWriteStart() are part of Eth library, used to read Phy registers 0-31 and should be available in your compiler.
with LAN 9303 they are using the same functions to read mapped registers - first two routines above do it.
Unmapped registers read/write use other two routines.

Re:TCP Stack support for LAN9303 (pluto55)

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Andy123, thanks a lot ,now I can read and write the register I need .

Re:TCP Stack support for LAN9303 (Andrew Frazer)

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Hi,  just wondering if there was any movement by Microchip to put the LAN9303 in the IP stack?

Re:TCP Stack support for LAN9303 (freebsd)

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Harmony v1.0 supports LAN9303  driver.
 
and it is available on the web.
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